Communications avec actes dans un congrès international

Computation of Wafer-At-Risk from Theory to Real Life Demonstration

  • Auteurs : M. Sahnoun Grenoble-INP G-SCOP, P. Vialletelle STMicroelectronics STMicroelectronics, J. Bassetto Grenoble-INP G-SCOP, M. Tollenaere Grenoble-INP G-scop, S. Bastoini STMicroelectronics STMicroelectronics
  • Conférence : Manufacturing Challenges in European Semiconductor Fabs, 18 novembre 2010
  • Ville : Rousset (France)
  • Mots clés : defectivity, skipping, Wafer-At-Risk, Wafer-At-Risk-Reduction

Over the past decade, control of process tools has progressively moved from bare non-product wafers inspection toward on-product measurements. Nevertheless, in high-mix facilities, recipe creation for all products is not possible. Most of the semiconductor fabs use today « high runners » lots that are flagged for defectivity. Due to non-linearity and variability of the line [1], lots may be stopped, overtake each-other or ignore certain tools. This is the drawback of this sampling method: the efficiency of the defectivity measurement with respect to information is often under optimal. On an other hand, the measurement equipments are very expensive and fabs are limited in capacity of inspection. Using the sampling method already quoted, we take the risk of controlling some lots unnecessarily. The aim of this study is to evaluate this risk and to propose a solution to optimize the use of control equipment. The case study described here takes place in STMicroelectronics 300mm wafer fab in Crolles, France. It considers the global fab toolset and studies the skip, under some assumptions, of a defectivity measurement. The Wafer-At-Risk is in use as the risk evaluation of each tool. The information brought by each lot that can be inspected is called the Wafer-At-Risk-Reduction. The problem is that this data is not directly available in fab, so, an algorithm was developed for the computation of the Wafer-At-Risk and Wafer-At-Risk-Reduction.

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